PCI Express FIFO interface

This is a work in progress. It is currently working well with speeds in excess of 1600 MB/s (4 lanes Gen 2). The Verilog module interface is not likely to change, but changes may be expected for some time in the internal logic and kernel driver that will break compatibility between the two.

Simple interfaces

The Harmon Instruments PCI Express FIFO core hides the complexity of the PCI Express transaction layer interface presented by the FPGA hard endpoint. Up to 4 in and 4 out FIFO interfaces are provided. These appear on the PC as device files (/dev/hififo__).

module hififo_pcie
   // IO pins
   output [`NLANES-1:0]    pci_exp_txp,
   output [`NLANES-1:0]    pci_exp_txn,
   input [`NLANES-1:0]     pci_exp_rxp,
   input [`NLANES-1:0]     pci_exp_rxn,
   input                   sys_clk_p,
   input                   sys_clk_n,
   input                   sys_rst_n,
   // from core
   output                  clock,
   // FIFOs
   input [7:0]             fifo_clock,
   output [7:0]            fifo_reset,
   input [7:0]             fifo_rw,
   output [7:0]            fifo_ready,
   output [63:0]           fifo_data_0,
   output [63:0]           fifo_data_1,
   output [63:0]           fifo_data_2,
   output [63:0]           fifo_data_3,
   input [63:0]            fifo_data_4,
   input [63:0]            fifo_data_5,
   input [63:0]            fifo_data_6,
   input [63:0]            fifo_data_7

Operating system support

A kernel module for Linux is provided as well as a user program demonstrating the core. Other operating systems are not currently supported.

Hififo on GitHub


The Harmon Instruments FPGA cores are licensed with the GPLv3. A commercial license may be negotiated upon request. For information, contact sales (at) harmoninstruments.com.

FPGA Compatibility

Currently, only Xilinx 7 series Integrated Block for PCI Express is supported (Artix-7, Kintex-7 and some Virtex-7). Other FPGAs with hard PCI Express endpoints may be added if sufficient demand exists.