OSHPark 4 Layer PCB Measurements

Intro

OSHPark PCBs are convenient for various RF test boards at a low cost given the relatively low loss Isola FR408 material. Trying an idea is much more appealing when the cost is $50 for the board and parts versus $1000+ for a custom RF material stack up prototype. As you will see there is some variation in properties over the board. These are built with prepreg for outer layers where RF and microwave PCBs typically have cores for outer layers for consistent dielectric thickness. These have been used succesfully at Harmon Instruments to beyond 50 GHz. Loss is extremely high at those frequencies, so lines must be kept short. There is a bypassable frequency doubler in the VNA that measured this data on an OSHPark PCB, providing stimulus from 26.5 GHz to 50 GHz.

Thanks to OSHPark for providing this board and the previous revisions at no charge.

The test board

The first revision used line widths calculated from the values on the OSHPark site. Impedances were consistenly high (56 ohms typical) over two orders of the board. This one uses the assumption of 0.19 mm thick prepreg with an Er of 3.3 (versus 0.17 mm and Er of 3.66) given in the OSHPark docs. See the previous blog post for the Er of just the material. The missing corner of this board was the sample used there. The prepreg in the cross section measures approximately 0.177 mm, but likely varies throughout the board. The total thickness varies about 25 µm over a board.

Microstrip

Time Domain

0.42 mm wide lines are used for 50 ohm microstrip on this board. As can be seen in the plot above, the impedanace is, on average, a bit low. Perhaps, 0.41 mm would be a good design value. PCB #1 had the most variation and the impedance correlates with PCB thickness variation along the line. There is a short thick area around the high impedance peak. The other two show a thickness taper along the length. I repeated the measurement of PCB #1 after #2 and #3 and got data nearly indistinguishable from the original measurement.

Using the same 0.42 mm width, but adding solder mask, gives a lower impedance of around 47 ohms. A good design value to achieve 50 ohms might be 0.39 mm. Covering microstrip in solder mask does save some insertion loss, but the difference is minimal, so unmasked may still be preferred.

Insertion loss (no solder mask)

Insertion loss (with solder mask)

Effective Relative Permittivity (Er)

Effective Er is simply the square of the speed of light divided by the propagation velocity in the line.

The unmasked microstrip should have an effective Er of around 2.5 given the assumptions about Er and the line geometry. It measures much higher. I presume this is due to metal loss and surface texture, but am not certain of it. Comments are welcome. I measure ErEff=1.002 for 3.5 mm air lines at 20 GHz using the same differential phase calculation. EM simulation shows that a textured conductor has slower propagation than a smooth one and this is rather rough copper. The plot below shows time domain step responses of both 53 mm lines with the masked line reaching 50% at 309.4 ps and the unmasked at 296.4 ps. Those correspond to effective Er values of 3.07 and 2.81. The effect of the mask slowing propagation is clearly visible. The stimulus rise time (10-90%), (set by the window function) is about 14 ps, masked is 25 ps and unmasked is 36 ps.

Stripline

The striplines on this board are 0.3 mm wide, on inner2, with copper on inner1 and the bottom as ground references. It's very close to 50 ohms. The vias need a bit more clearance (0.2 mm used on this board) as can be seen by the low impedance spikes in the time domain plot.

Time Domain

The 2.4/1.85 dip is the discontinuity resulting from the connection of a 2.4 mm and 1.85 mm connector. A similar discontinuity results from connecting a 2.92 to a 3.5 mm connector. The Harmon Instruments VNA supports removal of these discontinuities, but it was not enabled here. The via dips are the vias transitioning from microstrip to stripline.

Insertion Loss

The spikes at ~ 2 GHz intervals are artifacts of the LRL on PCB calibration (frequencies where the line phase difference is 180 degrees) and should be ignored. More lines could have been added to avoid these.

Effective Er

The Er of the core is about 4.0 and the prepreg 3.3. Electromagnetic simulation without metal loss gives an effective Er of 3.55 for this geometry. Like the microstrip case, these values are higher than expected. The values are higher at low frequencies primarily due to metal losses. Stripline is often stated to be free of dispersion, but that assumes lossless materials.

Components

This one is simply a 49.9 ohm 0402 resistor in series with 1 mm of 50 ohm line on either side and was done as a check on the impedance calibration. The result is as expected.

I'd previously measured these two ferrite beads with no DC bias, but had questioned how much that would change the inductance. The effect is significant at low frequency and small at higher frequencies. It's interesting that the order of the traces reverses above the self resonant frequency as the decreasing shunt inductance reduces the effective capacitance. These ferrite beads are mostly capacitive above the parallel resonance. The VNA bias tees contribute only a negligible amount (0.002 dB insertion loss increase at 200 mA) to this data.

These parts are both capacitive at higher frequencies and the above performance could be improved by adding short high impedance sections to either side of the ferrite bead. About 120 pH on either side should give the BLM15GG471 20 dB return loss to 30 GHz.